Author: Suvendu Das Adhikary

Digital Design/Verification Intern

Semifront is looking for folks who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad-level Microarchitecture and Architecture Specs. Skills and other requirements:- 1. Excellent/good Verilog/SystemVerilog/Perl Skillset 2. The coding will be Perl mixed Verilog/SV 3. Knowledge of Make, Python, Bash is an advantage, but not mandatory 4. The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory ...